Driving circuit electroluminescence cell

ABSTRACT

A driving circuit for an electro-luminescence (EL) cell includes an EL cell, and a supply circuit selectively applying current to the EL cell based on a pixel signal from a data line. A control circuit controls current flow from the supplying circuit to the EL cell such that an amount of current for discriminating between gray scale levels is approximately tens of micro-amps.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to an electro-luminescence display (ELD), andmore particularly to a driving circuit for driving electro-luminescencecells arranged on an electro-luminescence panel in a matrix type.

2. Description of the Related Art

Generally, an electro-luminescence (EL) panel converts an electricalsignal into light energy to thereby display a picture corresponding tovideo signals (or image signals). Such an EL panel includes EL cellsarranged at intersections between gate lines and data lines. Each of theEL cells responds to a pixel signal from the data line to generate alight corresponding to a magnitude of the pixel signal.

In order to stably apply a pixel signal to each EL cell, the EL panelhas cell-driving circuits scanned sequentially line-by-line. Each of theEL cell-driving circuits responds to a control signal at the gate lineto sample a pixel signal at the data line and then holds the sampledpixel signal during the next frame interval, to thereby stably apply thepixel signal to the EL cell.

As shown in FIG. 1, a conventional EL cell-driving circuit for carryingout such sampling and holding operations of a pixel signal includes afirst PMOS thin film transistor (TET) MP1 connected between an EL cellELC and a first node Ni. A gate of the first PMOS TFT MP1 is connectedto a second node N2, and the EL cell ELC is also connected to ground. Asecond PMOS TFT MP2 is connected between the second node N2 and the ELcell ELC, and is connected at its gate to a gate line GL. A capacitor C1is connected between the first and second nodes N1 and N2.

The capacitor C1 charges a voltage of a pixel signal when the pixelsignal is applied from a data line DL and applies the charged pixelvoltage to gate electrodes of the first PMOS TFT MP1. The first PMOS TETMP1 is turned on by the pixel voltage charged in the capacitor C1,thereby allowing a supply voltage VDD applied, via the first node Ni,from a voltage supply line VDDL to be supplied to the EL cell ELC.

At this time, the first PMOS TFT MP1 varies its channel width dependingon a voltage level of the pixel signal to control a current amountapplied to the EL cell ELC. Then, the EL cell ELC generates a lightcorresponding to the current amount applied from the first PMOS TFT MP1.The second PMOS TET MP2 responds to a gate signal GLS, as shown in FIG.2, applied from the gate line GL to selectively connect the second nodeN2 to the EL cell ELC.

More specifically, the second PMOS TFT MP2 connects the second node N2to the EL cell ELC at a time interval when the gate signal GLS isenabled at a low logic, thereby allowing the pixel signal to be chargedin the capacitor C1. In other words, the second PMOS TFT MP2 forms acurrent path of the capacitor C1 at a time interval when the gate signalGLS at the gate line GL is enabled. The capacitor C1 charges the pixelsignal in the enabling interval of the gate signal GLS, thereby allowingthe gate electrode of the first PMOS TFT MP1 to have a lower voltagethan the drain electrode by a voltage level of the charged pixel signal.Accordingly, a channel width of the first PMOS TFT MP1 is controlled inaccordance with a voltage level of the pixel signal to determine acurrent amount flowing from the first node N1 into the EL cell ELC.

The conventional EL cell driving circuit further includes a third PMOSTFT MP3, connected between the data line DL and the first node N1,responding to a gate signal at the gate line GL, and a fourth PMOS TFTMP4, connected between the voltage supply line VDDL and the first nodeN1, responding to an inverted gate signal /GLS from a gate bar line /GL.

The third PMOS TFT MP3 is turned on at a time interval when a low logicof gate signal is applied from the gate line GL, thereby connecting thecapacitor C1, coupled to the first node N1 and the source electrode ofthe first PMOS TFT MP1, to the data line DL. In other words, the thirdPMOS TFT MP3 responds to a low logic of gate signal GLS to send a pixelsignal at the data line DL to the first node N1. to the data line DL. Inother words, the third PMOS TFT M3 responds to a low logic of gatesignal GLS to send a pixel signal at the data line DL to the first nodeN1.

As a result, the third PMOS TFT MP3 is turned on during a time intervalwhen a gate signal at the gate line GL remains at a low logic, therebycharging a pixel signal into the capacitor C1 connected between thefirst and second nodes N1 and N2. The fourth PMOS TET MP4 is turned onin a time interval when a low logic of inverted gate signal /GLS fromthe gate bar line /GL is applied to the gate electrode thereof, therebyconnecting the first node N1, to which the capacitor C1 and the sourceelectrode of the first PMOS TFT MP1 are connected, to the voltage supplyline VDDL.

At a time interval when the fourth PMOS TET MP4 has been turned on, asupply voltage VDD at the voltage supply line VDDL is applied, via thefirst node N1 and the first PMOS TFT MP1, to the EL cell ELC. Thus, theEL cell ELC generates a light of a quantity according to a voltage levelof the pixel signal.

In the conventional EL cell driving circuit, a maximum current amount(i.e., a current margin of a pixel signal) required for obtaining amaximum brightness is small. For this reason, a current differencebetween gray scale levels of a video signal is approximately several μA.if a current difference between gray scale levels is set to several μA,a data driver integrated circuit (IC) chip must have the ability tocontrol current at a range of several μA accurately. However, it is verydifficult to manufacture a data driver IC chip capable of controlling acurrent at a range of several μA accurately. As a result, theconventional EL cell driving circuit has problems with driving theconventional EL panel to accurately display a gray scale of a picture.

SUMMARY OF THE INVENTION

The present invention provides a driving circuit for anelectro-luminescence cell that increases a current difference of a pixelsignal for identifying gray scale levels.

The present invention also provides an electro-luminescence panel thatmore accurately displays a gray scale of a picture.

In the electro-luminescence (EL) panel according to the presentinvention, the driving circuit for an electro-luminescence (EL) cellincludes an EL cell; a supply is circuit selectively applying current tothe EL cell based on a pixel signal from a data line; and a controlcircuit controlling current flow from the supplying circuit to the ELcell such that an amount of current for discriminating between grayscale levels is approximately tens of micro-amps.

According to an embodiment of the present invention, the supplyingcircuit includes a first transistor connected between the EL cell and avoltage supply line, and the control circuit includes a secondtransistor connected between the data line and the voltage supply linesuch that the first and second transistors form a current mirror. In apreferred embodiment, the second transistor has a channel width of 3 to20 times greater than a channel width of the first transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects of the invention will be apparent from thefollowing detailed description of the embodiments of the presentinvention with reference to the accompanying drawings, in which:

FIG. 1 is a circuit diagram showing a configuration of a driving circuitfor a conventional electro-luminescence cell;

FIG. 2 is a waveform diagram of driving signals applied to the gate lineand the gate bar line shown in FIG. 1; and

FIG. 3 is a circuit diagram showing a configuration of a driving circuitfor an electro-luminescence cell according to an embodiment of thepresent invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 3, there is shown a driving circuit for anelectro-luminescence (EL) cell according to an embodiment of the presentinvention.

The EL cell driving circuit includes an EL cell ELC connected to ground,and a first PMOS TFT MP1 connected between the EL cell ELC and a voltagesupply line VDDL. A second PMOS TFT MP2 is connected between a firstnode and the voltage supply line VDDL, and both of the gates of thefirst and second PMOS TFTs MP1 and MP2 are connected to a second nodeN2. The first and second PMOS TFTs MP1 and MP2 form a current mirrorbetween the first node N1 and the voltage supply line VDDL. A capacitorC is connected between the second node N2 and the voltage supply lineVDDL. Third and fourth PMOS TFTs MP3 and MP4 are connected in seriesbetween a data line DL and the second node N2. The gates of the thirdand fourth PMOS TFTs MP3 and MP4 are connected to a gate line GL.

The operation of the driving circuit in FIG. 3 will be describedassuming the third and fourth PMOS TFTs MP3 and MP4 are on. Then, theoperation of the third and fourth PMOS TFTs MP3 and MP4 will bedescribed.

The capacitor C charges to a difference voltage corresponding to adifference between a voltage of a pixel signal and a supply voltage VDDat the voltage supply line VDDL when the pixel signal is applied from adata line DL, and commonly applies the difference voltage to the gateelectrodes of the first and second PMOS TFTs MP1 and MP2. The first PMOSTFT MP1 is turned on by the difference voltage charged in the capacitorC and applies the supply voltage VDD at the voltage supply line VDDL tothe EL cell ELC. At this time, a channel width of the first PMOS TFT MP1is varied depending on a voltage level of the pixel signal to control anamount of current applied from the voltage supply line VDDL to the ELcell ELC. Then, the EL cell ELC generates light corresponding to theamount of current applied, via the first PMOS TFT MP1, from the voltagesupply line VDDL. Meanwhile, the second PMOS TFT MP2 controls a currentamount flowing from the voltage supply line VDDL into the data line DLwhen a pixel signal is applied from the data line DL, therebydetermining an amount of current applied to the EL cell ELC via thefirst PMOS TFT MP1.

A channel width of the second PMOS TFT MP2, which determines a currentamount flowing via the first PMOS TFT MP1 as mentioned above, is formedto be equal to several to tens of times the channel width of the firstPMOS TFT MP1. For instance, a channel width ratio of the first PMOS TFTMP1 to the second PMOS TFT MP2 may be in a range of 1:3 through 1:20. Tothe contrary, if the channel width ratio is in a range of 3:1 through10:1, then it has an advantage in power consumption. Making the channelwidths of the first and second PMOS TFTs MP1 and MP2 different from eachother as described above, increases an amount of the current differencein the pixel signal for discriminating gray scale levels toapproximately tens of μA. Even though a current amount flowing via thesecond PMOS TFT MP2 is varied at a difference of tens of μA by such apixel signal, a current amount applied, via the first PMOS TFT MP1having a channel width as small as several to tens of times the channelwidth of the second PMOS TFT MP2, to the EL cell ELC is varied at adifference of several μA. Accordingly, an EL panel driving IC chipdriving the data line DL can be made such that it generates a pixelsignal corresponding to a gray scale of video signal or image signal.Furthermore, the EL panel can display a gray scale of a picture with theaid of such a data line driving IC chip.

The third PMOS TFT MP3 is turned on at a time interval when a low logicof gate signal is applied from the gate line GL, thereby connecting thedrain electrode of the third PMOS TFT MP3 connected to the first node N1to the data line DL. In other words, the third PMOS TFT MP3 plays a roleto send a pixel signal at the data line DL in response to a tow logic ofthe gate signal. The fourth PMOS TFT MP4 also is turned on at a timeinterval when a low logic gate signal is applied from the gate line GLto the gate electrode thereof, thereby connecting the second node N2 viathe first node N1 to the data line DL. In other words, the third andfourth PMOS TFTs MP3 and MP4 are turned on at a time interval when agate signal at the gate line GL remains at a low logic, thereby chargingthe pixel signal into the capacitor C connected between the second nodeN2 and the voltage supply line VDDL.

As described above, according to the present invention, a channel widthof a PMOS TFT, forming part of a current mirror and responding to apixel signal, is enlarged by several to tens of times the channel widthof the other PMOS TFT in the current mirror that supplies current to theEL cell, thereby increasing an amount of the current difference in thepixel signal for discriminating gray scale levels. Accordingly, thepresent EL cell driving circuit permits manufacturing a data linedriving IC chip suitable for realizing a gray scale of a picture. Also,it permits an EL panel to accurately display a gray scale of a picture.

Although the present invention has been explained by the embodimentsshown in the drawings described above, it should be understood to theordinary skilled person in the art that the invention is not limited tothe embodiments, but rather that various changes or modificationsthereof are possible without departing from the spirit of the invention.For example, the PMOS transistors MP1 through MP4 included in theembodiment of the present invention shown in FIG. 3 can be replaced withNMOS transistors, In this case, the gate signal to be applied to thegate line GL has a waveform the same as /GLS of FIG. 2. Accordingly, thescope of the invention shall be determined only by the appended claimsand their equivalents.

1. A driving circuit for an electro-luminescence (EL) cell, comprising:an EL cell; a supply circuit selectively applying current to the EL cellbased on a pixel signal from a data line, the supply circuit including afirst transistor connected between the EL cell and a voltage supply lineand a charge storage device storing a charge based on the pixel signal;and a control circuit controlling current flow from the supply circuitto the EL cell, the control circuit including a second transistorconnected between the data line and the voltage supply line such thatthe first and second transistors form a current mirror, the first andsecond transistors having gates connected to the charge storagedevice.device; a third transistor connected between a data supply lineand the second transistor, and a gate of the third transistor connectedto a gate signal supply line; a first node connected between the thirdtransistor and the second transistor; and a fourth transistor connectedbetween the first node and the gate of the first transistor and betweenthe first node and the gate of the second transistor, and a gate of thefourth transistor connected to the gate signal supply line.
 2. Thedriving circuit of claim 1, wherein the second transistor has a channelwidthof-to-length ratio that is 3 to 20 times greater than a channelwidth-to-length ratio of the first transistor.
 3. The driving circuit ofclaim 2 1, wherein the first transistor has a channel widthof-to-lengthratio that is 3 to 10 times greater than a channel width-to-length ratioof the second transistor.
 4. The driving circuit of claim 1, furthercomprising: a third transistor connected between a data supply line andthe second transistor, and a gate of the third transistor connected to agate signal supply line; and a fourth transistor connected between thethird transistor and the gates of the first and second transistors, anda gate of the fourth transistor connected to the gate signal supplyline.
 5. The driving circuit of claim 1, further comprising: an enablecircuit selectively connecting the supply and control circuits to thedata line based on a gate signal.
 6. An electrode luminescence panelcomprising the driving circuit for the electro-luminescence cell asdescribed in claim
 1. 7. The driving circuit of claim 1, wherein anamount of current for discriminating between gray scale levels isapproximately tens of micro-amps.
 8. A driving circuit for anelectro-luminescence (EL) cell, comprising: an EL cell; a supply circuitselectively applying current to the EL cell based on a pixel signal froma data line, the supply circuit including a first transistor connectedbetween the EL cell and a voltage supply line and receiving a voltagedependent on the pixel signal at a gate thereof; a control circuitcontrolling current flow from the supplying circuit to the EL cell, thecontrol circuit including a second transistor connected between the dataline and the voltage supply line and a gate of the second transistorbeing connected to the gate of the first transistor; and a thirdtransistor connected between a data supply line and the secondtransistor, and a gate of the third transistor connected to a gatesignal supply line; a first node connected between the third transistorand the second transistor; a fourth transistor connected between thefirst node and the gate of the first transistor and between the firstnode and the gate of the second transistor, and a gate of the fourthtransistor connected to the gate signal supply line; and a chargestorage device connected between the gates of the first and secondtransistors and the voltage supply line.
 9. The driving circuit of claim8, wherein the second transistor has a channel widthof-to-length ratiothat is 3 to 20 times greater than a channel width-to-length ratio ofthe first transistor.
 10. The driving circuit of claim 9 8, wherein thefirst transistor has a channel widthof-to-length ratio that is 3 to 10times greater than a channel width-to-length ratio of the secondtransistor.
 11. The driving circuit of claim 8, further comprising: athird transistor connected between a data supply line and the secondtransistor, a gate of the third transistor connected to a gate signalsupply line; and a fourth transistor connected between the thirdtransistor and the gates of the first and second transistors, a gate ofthe fourth transistor connected to a gate signal supply line.
 12. Adriving circuit for an electro-luminescence (EL) cell, comprising: an ELcell; a current mirror including a first and a second transistor, thefirst transistor supplying current to the EL cell based on a pixelsignal, and the second transistor controlling the supply of currentthrough the first transistor, the first and second transistors havinggates connected to a charge storage device.device; a third transistorconnected between a data supply line and the second transistor, and agate of the third transistor connected to a gate signal supply line; afirst node connected between the third transistor and the secondtransistor; and a fourth transistor connected between the first node andthe gate of the first transistor and between the first node and the gateof the second transistor, and a gate of the fourth transistor connectedto the gate signal supply line.
 13. The driving circuit of claim 12,wherein the a channel width-to-length ratio of the first transistor is 3to 10 times greater than the a channel width-to-length ratio of thesecond transistor.
 14. The driving circuit of claim 12, furthercomprising: an enabling circuit selectively enabling operation of thecurrent mirror based on a gate signal.
 15. A The driving circuit ofclaim 12, wherein the second transistor has a channel width-to-lengthratio that is 2 to 20 times greater than a channel width-to-length ratioof the first transistor.
 16. A driving circuit for anelectro-luminescence (EL) cell, comprising: an EL cell; and a currentmirror including a first transistor and a second transistor, the firsttransistor supplying current to the EL cell based on a pixel signal, andthe second transistor controlling the supply of current through thefirst transistor, a channel width-to-length ratio of the secondtransistor formed to be a ratio of a channel width-to-length ratio ofthe first transistor.transistor; a third transistor connected between adata supply line and the second transistor, and a gate of the thirdtransistor connected to a gate signal supply line; a first nodeconnected between the third transistor and the second transistor; and afourth transistor connected between the first node and the gate of thefirst transistor and between the first node and the gate of the secondtransistor, and a gate of the fourth transistor connected to the gatesignal supply line.
 17. The driving circuit of claim 1, wherein thesecond transistor has a current capacity greater than a current capacityof the first transistor.
 18. The driving circuit of claim 1, wherein thefirst transistor has a current capacity greater than a current capacityof the second transistor.
 19. The driving circuit of claim 1, whereinthe second transistor has a channel dimension greater than a channeldimension of the first transistor.
 20. The driving circuit of claim 1,wherein the first transistor has a channel dimension greater than achannel dimension of the second transistor.
 21. The driving circuit ofclaim 1, wherein the second transistor has a channel width-to-lengthratio that is greater than a channel width-to-length ratio of the firsttransistor.
 22. The driving circuit of claim 1, wherein the firsttransistor has a channel width-to-length ratio that is greater than achannel width-to-length ratio of the second transistor.
 23. The drivingcircuit of claim 8, wherein the second transistor has a current capacitygreater than a current capacity of the first transistor.
 24. The drivingcircuit of claim 8, wherein the first transistor has a current capacitygreater than a current capacity of the second transistor.
 25. Thedriving circuit of claim 8, wherein the second transistor has a channeldimension greater than a channel dimension of the first transistor. 26.The driving circuit of claim 8, wherein the first transistor has achannel dimension greater than a channel dimension of the secondtransistor.
 27. The driving circuit of claim 8, wherein the secondtransistor has a channel width-to-length ratio that is greater than achannel width-to-length ratio of the first transistor.
 28. The drivingcircuit of claim 8, wherein the first transistor has a channelwidth-to-length ratio that is greater than a channel width-to-lengthratio of the second transistor.
 29. The driving circuit of claim 12,wherein the second transistor has a current capacity greater than acurrent capacity of the first transistor.
 30. The driving circuit ofclaim 12, wherein the first transistor has a current capacity greaterthan a current capacity of the second transistor.
 31. The drivingcircuit of claim 12, wherein the second transistor has a channeldimension greater than a channel dimension of the first transistor. 32.The driving circuit of claim 12, wherein the first transistor has achannel dimension greater than a channel dimension of the secondtransistor.
 33. The driving circuit of claim 12, wherein the secondtransistor has a channel width-to-length ratio that is greater than achannel width-to-length ratio of the first transistor.
 34. The drivingcircuit of claim 12, wherein the first transistor has a channelwidth-to-length ratio that is greater than a channel width-to-lengthratio of the second transistor.
 35. The driving circuit of claim 16,wherein the second transistor has a current capacity greater than acurrent capacity of the first transistor.
 36. The driving circuit ofclaim 16, wherein the first transistor has a current capacity greaterthan a current capacity of the second transistor.
 37. The drivingcircuit of claim 16, wherein the second transistor has a channeldimension greater than a channel dimension of the first transistor. 38.The driving circuit of claim 16, wherein the first transistor has achannel dimension greater than a channel dimension of the secondtransistor.
 39. The driving circuit of claim 16, wherein the secondtransistor has a channel width-to-length ratio that is greater than achannel width-to-length ratio of the first transistor.
 40. The drivingcircuit of claim 16, wherein the first transistor has a channelwidth-to-length ratio that is greater than a channel width-to-lengthratio of the second transistor.